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lm5072 integrated 100v power over ethernet pd interface and pwm controller with aux support general description the lm5072 powered device (pd) interface and pulse- width-modulation (pwm) controller provides a complete power solution, fully compliant to ieee 802.3af, for the pd connecting into power over ethernet (poe) networks. this controller integrates all functions necessary to implement both a pd powered interface and dc-dc converter with a minimum number of external components. the lm5072 pro- vides the flexibility for the pd to also accept power from auxiliary sources such as ac adapters in a variety of con- figurations. the low rds(on) pd interface hot swap mos- fet and programmable dc current limit extend the range of lm5072 applications up to twice the power level of 802.3af compliant pd devices. the 100v maximum voltage rating simplifies selection of the transient voltage suppressor that protects the pd from network transients. the lm5072 in- cludes an easy-to-use pwm controller that facilitates the various single-ended power supply topologies including the flyback, forward and buck. the pwm control scheme is based on peak current mode control, which provides inher- ent advantages including line feed-forward, cycle-by-cycle current limit, and simplified feedback loop compensation. two versions of the lm5072 provide either an 80% maxi- mum duty cycle (-80 suffix), or a 50% maximum duty cycle (-50 suffix). features pd interface n fully compliant ieee 802.3af pd interface n versatile auxiliary power options n 9v minimum auxiliary power operating range n 100v maximum input voltage rating n programmable dc current limit up to 800ma n 100v, 0.7 ? hot swap mosfet n integrated pd signature resistor n integrated poe input uvlo n programmable inrush current limit n pd classification capability n power good indicator n thermal shutdown protection pwm controller n current mode pwm controller n 100v start-up regulator n error amplifier with 2% voltage reference n supports isolated and non-isolated applications n programmable oscillator frequency n programmable soft-start n 800 ma peak gate driver n 80% maximum duty cycle with built-in slope compensation (-80 device) n 50% maximum duty cycle, no slope compensation (-50 device) applications n ieee 802.3af compliant poe powered devices n non-compliant, application specific devices n higher power ethernet powered devices packages n tssop-16 ep (exposed pad) simplified application diagram 20184601 march 2006 lm5072 integrated 100v power over ethernet pd interface and pwm controller with aux support 2006 national semiconductor corporation ds201846 www.national.com
connection diagram 20184602 16 lead tssop-ep ordering information order number description nsc package type / drawing supplied as lm5072mh-50 50% duty cycle limit tssop-16ep/mxa16a 92 units per rail lm5072mhx-50 50% duty cycle limit tssop-16ep/mxa16a 2500 units on tape and reel LM5072MH-80 80% duty cycle limit tssop-16ep/mxa16a 92 units per rail lm5072mhx-80 80% duty cycle limit tssop-16ep/mxa16a 2500 units on tape and reel lm5072 www.national.com 2
pin descriptions pin number name description 1 rt pwm controller oscillator frequency programming pin. 2 ss soft-start programming pin. 3 vin positive supply pin for the pd interface and the internal pwm controller start-up regulator. 4 rclass pd classification programming pin. 5 icl_faux inrush current limit programming pin; also the front auxiliary power enable pin. 6 dccl pd interface dc current limit programming pin. 7 vee negative supply pin for pd interface; connected to poe and/or front auxiliary power return path. 8 rtn pwm controller power return; connected to the drain of the internal pd interface hot swap mosfet; should be externally connected to the reference ground of the pwm controller. 9 out pwm controller gate driver output pin. 10 vcc pwm controller start-up regulator output pin. 11 npgood pd interface power good indicator and delay timer pin; active low state indicates poe interface is in normal operation. 12 cs pwm controller current sense input pin. 13 raux rear auxiliary power enable pin; can be programmed for auxiliary power dominance over poe power. 14 fb pwm controller voltage feedback pin and inverting input of the internal error amplifier; connect to artn to disable the error amplifier in isolated dc-dc converter applications. 15 comp output of the internal error amplifier and control input to the pwm comparator. in isolated applications, comp is controlled by the secondary side error amplifier via an opto-coupler. 16 artn pwm controller reference ground pin; should be shorted externally to the rtn pin as a single point ground connection to improve noise immunity. ep exposed metal pad on the underside of the device. it is recommended to connect this pad to a pc board plane connected to the vee pin to improve heat dissipation. lm5072 www.national.com 3
absolute maximum ratings (note 1) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. vin , rtn to vee (note 7) -0.3v to 100v raux to artn -0.3v to 100v icl_faux to vee -0.3v to 100v dccl, rclass to vee -0.3v to 7v npgood to artn -0.3v to 16v artn to rtn -0.3v to 0.3v vcc, out to artn -0.3v to 16v cs, fb, rt to artn -0.3v to 7v comp, ss to artn -0.3v to 5.5v esd rating human body model (note 2) 2000v lead soldering temp. (note 3) wave (4 seconds) infrared (10 seconds) vapor phase (75 seconds) 260?c 240?c 219?c storage temperature -55?c to 150?c junction temperature 150?c operating ratings v in voltage 9v to 70v external voltage applied to v cc 8v to 15v operating junction temperature -40?c to 125?c electrical characteristics (note 4) specifications in standard type face are for t j = +25?c and those in boldface type apply over the full operating junction temperature range. unless otherwise specified: v in = 48v, f osc = 250khz. symbol parameter conditions min typ max units detection and classification v in signature startup voltage 1.5 v signature resistance 23.25 24.5 26 k ? signature resistor disengage/ classification engage v in rising 11.0 12.0 12.6 v hysteresis 1.9 v classification current turn off v in rising 22 23.5 25 v classification voltage 1.213 1.25 1.287 v supply current during classification v in = 17v 0.7 1.1 ma line under voltage lock-out uvlo release v in rising 36 38.5 40 v uvlo lock out v in falling 29.5 31.0 32.5 v uvlo hysteresis 6 v uvlo filter 300 ? power good vds required for power good status 1.3 1.5 1.7 v vds hysteresis of power good status 0.8 1.0 1.2 v vgs required for power good status 4.5 5.5 6.5 v default delay time of loss-of power good status 30 ? npgood current source 45 55 65 ? npgood pull down resistance 130 250 ? npgood threshold 2.3 2.5 2.7 v hot swap rds(on) hot swap mosfet resistance 0.7 1.2 ? hot swap mosfet leakage 110 ? default inrush current limit v ds = 4.0v 120 150 180 ma default dc current limit v ds = 4.0v 380 440 510 ma front auxiliary dc current limit v ds = 4.0v 470 540 610 ma inrush current limit programming accuracy v ds = 4.0v -15 15 % dc current limit programming accuracy v ds = 4.0v -12 12 % lm5072 www.national.com 4
electrical characteristics (note 4) specifications in standard type face are for t j = +25?c and those in boldface type apply over the full operating junction temperature range. unless otherwise specified: v in = 48v, f osc = 250khz. (continued) symbol parameter conditions min typ max units auxiliary power option icl_faux threshold icl_faux pin rising 8.1 8.7 9.3 v icl_faux pull down current 50 ? raux lower threshold (i = 22 ?) raux pin rising 2.3 2.5 3.0 v raux upper threshold (i = 250 ?) raux pin falling 5.4 6.0 6.9 v raux lower threshold hysteresis 0.8 v raux lower threshold current 16 22 28 ? raux upper threshold current 187 250 313 ? vcc regulator vccreg vcc regulation (vccreg) 7.4 7.7 8 v vcc current limit 15 ma vcc uvlo (rising) vccreg ? 210 mv vccreg 100 mv v vcc uvlo (falling) 5.9 6.2 6.5 v vin supply current v cc = 10v 2.0 ma supply current (icc) v cc = 10v 3 ma vcc regulator dropout v in ? cc (note 6) 6.5 v error amplifier gain bandwidth 3 mhz dc gain 67 db input voltage 1.225 1.275 v comp sink capability 5 10 ma current limit ilim delay to output 30 ns cycle by cycle current limit threshold voltage 0.45 0.5 0.55 v leading edge blanking time 65 ns cs sink impedance (clocked) 35 55 ? soft-start soft-start current source 8 10 12 ? oscillator frequency1 (r t = 26.1 k ? ) 175 200 225 khz frequency2 (r t = 8.7 k ? ) 515 580 645 khz sync threshold 2.6 3.2 3.8 v pwm comparator delay to output 25 ns min duty cycle 0 % max duty cycle (-80 device) 75 80 85 % max duty cycle (-50 device) 47 50 53 % comp to pwm comparator gain 0.33 comp open circuit voltage 4.3 5.2 6.1 v comp short circuit current 0.6 1.0 1.4 ma slope compensation (lm5072-80 device only) slope comp amplitude 70 90 110 mv output section output high saturation 0.25 0.75 v lm5072 www.national.com 5
electrical characteristics (note 4) specifications in standard type face are for t j = +25?c and those in boldface type apply over the full operating junction temperature range. unless otherwise specified: v in = 48v, f osc = 250khz. (continued) symbol parameter conditions min typ max units output low saturation 0.25 0.75 v t r rise time c load = 1nf 18 ns t f fall time c load = 1nf 15 ns pdi thermal shutdown (note 5) thermal shutdown temp. 165 ?c thermal shutdown hysteresis 25 ?c thermal resistance ja junction to ambient mxa package 125 ?c/w note 1: absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions under which operation of the device is intended to be functional. for guaranteed specifications and test conditions, see the electrical characteristics. note 2: the human body model is a 100 pf capacitor discharged through a 1.5 k ? resistor into each pin. note 3: for detailed information on soldering the plastic tssop package, refer to the packaging databook available from national semiconductor. note 4: minimum and maximum limits are guaranteed through test, design, or statistical correlation using statistical quality control (sqc) methods. typic al values represent the most likely parametric norm at t j = 25?c, and are provided for reference purpose only. limits are used to calculate nationals average outgoing quality level (aoql). note 5: device thermal limitations may limit usable range. note 6: the vcc regulator is intended for use solely as a bias supply for the lm5072, dropout assumes 3ma of external v cc current. note 7: during rear auxiliary operation, the rtn pin can be approximately -0.4v with respect to vee. this is caused by normal internal bias currents, and will n ot harm the device. application of external voltage or current must not cause the absolute maximum rating to be exceeded. lm5072 www.national.com 6
typical performance characteristics uvlo threshold vs temperature default current limit vs temperature 20184603 20184604 inrush current limit vs icl_faux resistor dc current limit vs. dccl resistor 20184605 20184606 programmed dc current limit vs temperature oscillator frequency vs temperature 20184607 20184608 lm5072 www.national.com 7
typical performance characteristics (continued) oscillator frequency vs rt resistance error amplifier reference voltage vs temperature 20184609 20184610 v cc vs i cc input current vs input voltage 20184611 20184612 maximum duty cycle vs temperature soft-start current vs temperature 20184613 20184614 lm5072 www.national.com 8
specialized block diagrams 20184615 figure 1. top level block diagram lm5072 www.national.com 9
specialized block diagrams (continued) description of operation and applications information the lm5072 integrates a fully ieee 802.3af compliant pd interface and pwm controller in a single integrated circuit, providing a complete and low cost power solution for devices that connect to poe systems. the implementation requires a minimal number of external components. the lm5072s hot swap pd interface provides four major advantages: 1. an input voltage rating up to 100v that allows greater flexibility when selecting a transient surge suppressor to protect the pd from voltage transients encountered in poe applications. 2. the integration of the pd signature resistor and other functions including programmable inrush current limit, input voltage under-voltage lock-out (uvlo), pd classi- fication, and thermal shutdown simplifies pd implemen- tation. 3. the pd interface and pwm controller accept power from auxiliary sources including ac adapters and solar cells in various configurations and over a wide range of input voltages. auxiliary power input can be programmed to be dominant over poe power. 4. dc current limit is programmable and adjustable to sup- port poe applications requiring input currents up to 700 ma. the lm5072 includes an easy to use pwm controller based on the peak current mode control technique. current mode control provides inherent advantages such as line voltage feed-forward, cycle-by-cycle current limit, and simplified closed-loop compensation. the controllers pwm gate driver is capable of sourcing and sinking peak currents of 800 ma to directly drive the power mosfet switch of the dc-dc converter. the pwm controller also contains a high gain, high bandwidth error amplifier, a high voltage startup bias regulator, a programmable oscillator for a switching fre- quency between 50 khz to 500 khz, a bias supply (v cc ) under-voltage lock-out circuit, and a programmable soft-start circuit. these features greatly simplify the design and imple- mentation of single ended topologies like the flyback, for- ward and buck. the lm5072 is available in two versions, the lm5072-50 and lm5072-80. as indicated in the suffix of the part number, the maximum duty cycle of each device is limited to 50% and 80%, respectively. internal pwm controller slope compensa- tion is provided in the lm5072-80 version. 20184616 figure 2. pwm controller block diagram lm5072 www.national.com 10
modes of operation per the ieee 802.3af specification, when a pd is connected to a poe system it transitions through several operating modes in sequence including detection, classification (op- tional), turn on, normal operation, and power removal. each operating mode corresponds to a specific poe voltage range fed through the ethernet cable. figure 3 shows the ieee 802.3af specified sequence of operating modes and the corresponding pd input voltages. current steering diode-bridges are required for the pd inter- face to accept all allowable connections and polarities of poe voltage from the rj-45 connector (see the example application circuits in figures 18, 19, 20 and 21). the bridge will cause some reduction of the input voltage sensed by the lm5072. to guarantee full compliance to the specification in all operating modes, the lm5072 takes into account the voltage drop across the bridge diodes and responds appro- priately to the voltage received from the poe cable. table 1 presents the response in each operating mode to voltages across the vin and vee pins. table 1. operating modes with respect to input voltage mode of operation voltage from poe cable per ieee 802.3af lm5072 input voltage (v in pin to v ee pin) detection (signature) 2.7v to 10.0v 1.5v to 10.0v classification 14.5v to 20.5v 12v to 23.5v startup 42v max 38v (uvlo release, v in rising) normal operation 57v to 36v 75v to 32v (uvlo, v in falling) 20184617 figure 3. sequence of poe operating modes lm5072 www.national.com 11
detection signature during detection mode, a pd must present a signature re- sistance between 23.75 k ? and 26.25 k ? to the poe power sourcing equipment. this signature impedance distinguishes the pd from non-poe capable equipment to protect the latter from being accidentally damaged by inadvertent application of poe voltage levels. to simplify the circuit implementation, the lm5072 integrates the 24.5 k ? signature resistor, as shown in figure 4. during detection mode, the voltage across the vin and vee pins is less than 10v. once signature mode is complete, the lm5072 will disengage the signature resistor to reduce power loss in all other modes. classification classification is an optional feature of the ieee802.3af specification. it is primarily used to identify the power re- quirements of a particular pd device. this feature will allow the pse to allocate the appropriate available power to each device on the network. classification is performed by mea- suring the current flowing into the pd during this mode. ieee 802.3af specifies five power classes, each corresponding to a unique range of classification current, as presented in table 2. the lm5072 simplifies the classification implemen- tation by requiring a single external resistor connected be- tween the rclass and vee pins to program the classifica- tion current. the resistor value required for each class is also given in table 2. table 2. classification levels and required external resistor value class pd max power level iclass range lm5072 rclass value from to from to 0 (default) 0.44w 12.95w 0 ma 4 ma open 1 0.44w 3.84w 9 ma 12 ma 130 ? 2 3.84w 6.49w 17 ma 20 ma 71.5 ? 3 6.49w 12.95w 26 ma 30 ma 46.4 ? 4 reserved reserved 36 ma 44 ma 31.6 ? figure 5 shows the lm5072s implementation of pd classi- fication using an external resistor connected to the rclass pin. during classification, the voltage across the vin and vee pins is between 13v and 23.5v. in this voltage range, the class resistor rclass is engaged by enabling the 1.25v buffer amplifier and mosfet. after classification is com- plete, the voltage from the pse will increase to the normal operating voltage of the poe system (48v nominal). when v in rises above 23.5v, the lm5072 will disengage the rclass resistor to reduce on-chip power dissipation. the classification feature is disabled when either the front or rear auxiliary power options are selected, as the classifica- tion function is not required when power is supplied from an auxiliary source. the classification function is also disabled when the lm5072 reaches the thermal shutdown tempera- ture threshold (nominally 165?c). this may occur if the 20184618 figure 4. detection circuit with integrated pd signature resistor 20184619 figure 5. pd classification ? fulfilled with a single external resistor lm5072 www.national.com 12
classification (continued) lm5072 is operated at elevated ambient temperatures and the classification time exceeds the ieee802.3af limit of 75 ms. when the classification option is not required, simply leave the rclass pin open to set the pd to the default class 0 state. class 0 requires that the pse allocate the maximum ieee802.3af specified power of 15.4 w (12.95 w at the pd input terminals) to the pd. undervoltage lockout (uvlo) the lm5072s internal preset uvlo circuit continuously monitors the poe input voltage between the vin and vee pins. when the v in voltage rises above 38v nominal, the uvlo circuit will release the hot swap mosfet and initiate the startup inrush sequence. when the v in voltage falls below 31v nominal during normal operating mode, the lm5072 disables the pd by shutting off the hot swap mosfet. figure 6 illustrates the block diagram of the lm5072 uvlo circuit. this function requires no external components. the uvlo signal can be over-ridden by the front auxiliary power option (see details in the faux section) to allow the hot swap mosfet of the lm5072 to pass power from front auxiliary power sources at voltage levels below the poe operating voltage. in the rear auxiliary power application (see raux section), the auxiliary power source bypasses the hot swap mosfet and is applied directly to the input of the dc-dc converter. the uvlo function does not need to be over-ridden in this configuration. the pd can draw a maximum current of 400 ma during standard 802.3af poe operation. this current will cause a voltage drop of up to 8v over a 100m long ethernet cable. the pd front-end current steering diode bridges may intro- duce an additional 2v drop. in order to guarantee successful startup at the minimum poe voltage of 42v, and to continue operation at the minimum requirement of 36v as specified by ieee 802.3af, these voltage drops must be taken into ac- count. therefore, the lm5072 uvlo thresholds have been set to 38v on the rising edge of vin, and 31v on the falling edge of vin. the 7v nominal hysteresis of the uvlo func- tion, in addition to the inrush current limit (discussed in the next section), prevents false starts and chattering during startup. inrush current limit programming according to ieee 802.3af, the input capacitance of the pd power supply must be at least 5 f (between the vin and rtn pins). considering the capacitor tolerance and the ef- fects of voltage and temperature, a nominal capacitor value of at least 10 ? is recommended to ensure 5 f minimum under all conditions. a greater amount of capacitance may be needed to filter the input ripple of the dc-dc converter. the input capacitors remain discharged during detection and classification modes of the pd interface. the hot swap mos- fet is turned on after the vin minus vee voltage difference rises above the uvlo release threshold of 38v nominal. when enabled, the hot swap mosfet delivers a regulated inrush current to charge the input capacitors of the dc-dc converter. to prevent excessive inrush current, the lm5072 20184620 figure 6. preset input uvlo function lm5072 www.national.com 13
inrush current limit programming (continued) will turn on the hot swap mosfet in a constant current mode. the default, pre-programmed inrush current of 150 ma can be selected by simply leaving the icl_faux pin open. to adjust the capacitor charging time for a particular appli- cation requirement, the inrush limit can be programmed to any value between 150 and 400 ma with an external resistor (r icl ) between the icl_faux and vee pins, as shown in figure 7. the relationship between the r icl value and the desired inrush current limit i inrush satisfies the following equation: the inrush current causes a voltage drop along the poe ethernet cable (20 ? maximum) that reduces the input volt- age sensed by the lm5072. to avoid erratic turn-on (hic- cups), i inrush should be programmed such that the input voltage drop due to cable resistance does not exceed the v in-uvlo hysteresis (6v minimum). dc current limit programming the lm5072 provides a default dc current limit of 440 ma nominal. this default limit can be selected by leaving the dccl pin open. the lm5072 allows the dc current limit to be programmed within the range from 150 ma to 800 ma. figure 8 shows the method to program the dc current limit with an external resistor, r dccl . the relationship between the r dccl value and the desired dc current limit i dc satisfies the following equation: the maximum recommended dc current limit is 800 ma. while thermal analysis should be a standard part of the module development process, it may warrant additional at- tention if the dc current limit is programmed to values in excess of 400 ma. this analysis should include evaluations of the dissipation capability of lm5072 package, heat sinking properties of the pc board, ambient temperature, and other heat dissipation factors of the operating environment. power good and regulator startup the power good status indicates that the circuit is ready for pwm controller startup to occur. it is established when the input capacitors are fully charged through the hot swap mosfet. since the hot swap mosfet is in series with the input capacitors of the dc-dc converter, its drain-to-source voltage decreases as the charging occurs. power good is indicated when the following two conditions are met: the mosfet drain-to-source voltage drops below 1.5v (with 1v hysteresis), and the gate-to-source voltage is greater than 5v. circuitry internal to the lm5072 monitors both the drain and gate voltages (see figure 1), and issues the power good status flag by pulling down the npgood pin to a logic low level relative to the artn pin. the npgood circuitry consists of a 2.5v comparator, a 130 ? pull down mosfet, and a 50 a pull up current source, as shown in figure 9. once the power good status is established, the npgood pin voltage will be pulled down quickly by the mosfet, and the pwm controller will start as soon as the npgood pin voltage drops below the 2.5v threshold. 20184622 figure 7. input inrush limit programming via r icl 20184624 figure 8. input dc current limit programming via r dccl lm5072 www.national.com 14
power good and regulator startup (continued) the npgood pin can be configured to perform multiple functions. as shown in figure 9, it can be used to implement a ?owered from poe indicator using an led with a series current limiting resistor connected to the vcc pin. this may be useful when the auxiliary power source is directly con- nected to the dc-dc converter stage, a situation known as ?aux (see auxiliary power options below). in such a configuration, the npgood pin will be active when the pd is operating from poe power but not when it is powered from the auxiliary source. however, the ?owered from poe indi- cator is not applicable in systems implementing the front auxiliary power configuration ?aux (see auxiliary power options below) because both poe and auxiliary supply cur- rent pass through the hot swap mosfet. in this configura- tion, the npgood pin is active when either poe power or auxiliary power is applied. the designer should ensure that the current drawn by the led is not more than a few milli- amps, as the v cc regulators output current is limited to 15 ma and must also supply the lm5072s bias current and external mosfets gate charging current. supplying an external v cc that is higher than the regulated level with a bench supply is an easy way to measure vcc load during normal operation. it should also be noted that an external load on the v cc line will increase the dropout voltage of the v cc regulator. this may be a concern when operating from a low voltage rear auxiliary supply. the npgood pin can also be used to implement a delay timer by adding a capacitor from the npgood pin to the artn pin. this delay timer will prevent the interruption of the pwm controllers operation in the event of an intermittent loss of power good status. this can be caused by poe line voltage transients that may occur when switching between normal poe power and a backup supply system (e.g. a battery or ups). this condition will create a new ?ot swap event if there is a voltage difference between the backup supply and poe supply. since the hot swap mosfet will likely limit current during such a sudden input voltage change, the npgood pin will momentarily switch to the ?ull up state. a capacitor on this pin will delay the transition of the npgood pin state in order to provide continuous opera- tion of the pwm controller during such transients. the power good filter delay time and capacitor value can be selected with the following equation: for example, selecting 1000 nf for c pgood , the delay time will be 50 ms if no led is used and about 0.83 ms when an led, drawing 3 ma, is used. the delay required for contin- ued operation will depend on the amplitude of the transient, the dc current limit, the load, and the total amount of input capacitance. note that this delay does not guarantee contin- ued operation. if the hot swap mosfet is in current limit for an extended period, it may cause a thermal limit condition. this will result in a complete shutdown of the switching regulator, though no elements in the system will be perma- nently damaged and normal operation will resume momen- tarily. the power good status will also affect the default dc cur- rent limit. should the sensed drain to source voltage of the hot swap mosfet (from artn to v ee ) exceed 2.5v, the lm5072 will increase the dc current limit from the default 440 ma to 540 ma, thus allowing the pd to continue opera- tion through the transient event. this higher current limit will remain in effect until one of the following events occur: (i) the duration of loss of power good status exceeds t pg_delay ,at which time the pwm controller will be disabled, (ii) the increased power dissipation in the hot swap mosfet causes a thermal limit condition as previously discussed, or (iii) the mosfet drain to source voltage falls below 1.5v to re-establish power good status. under this condition, the lm5072 will revert back to the default 440 ma dc current limit once power good status is restored. note that if the dc current limit has been programmed externally with r dccl (see the dc current limit section), the dc current limit will remain at the programmed level even when the power good status is lost. 20184625 figure 9. "powered-from-poe" indictor and power good delay timer lm5072 www.national.com 15
auxiliary power options the lm5072 based pd can receive power from auxiliary sources like ac adapters and solar cells in addition to the poe enabled network. this is a desirable feature when the total system power requirements exceed the pses load capacity. furthermore, with the auxiliary power option the pd can be used in a standard ethernet (non-poe) system. for maximum versatility, the lm5072 accepts two different auxiliary power configurations. the first one, shown in figure 10, is the front auxiliary (faux) configuration in which the auxiliary source is ?iode or? with the poe potential re- ceived from the ethernet connector. the second configura- tion, shown in figure 11, is the rear auxiliary (raux) option in which the auxiliary power bypasses the poe interface and is connected directly to the input of the dc-dc converter through a diode. the faux option is desirable if the auxiliary power voltage is similar to the poe input voltage. however, when the auxiliary supply voltage is much lower than the poe input voltage, the raux option is more favorable be- cause the current from the auxiliary supply is not limited by the hot swap mosfet dc current limit. a comparison of the faux and raux options is presented in table 3. note the icl_faux and raux pins are not reverse voltage pro- tected. if complete reverse protection is desired, series blocking diodes are necessary. 20184627 figure 10. the faux configuration 20184628 figure 11. the raux configuration lm5072 www.national.com 16
auxiliary power options (continued) table 3. comparison between faux and raux operation tradeoff faux operation raux operation hot swap protection / current limit protection automatically provided by the hot swap mosfet. requires a series resistor to limit the inrush current during hot swap. minimum auxiliary voltage (at the ic pins) limited to 18v by the signature detection mode, or by the power requirement (current limit). only limited by 9v minimum input requirement. auxiliary dominance over poe cannot be forced without external components. can be forced with appropriate raux pin configuration. use of npgood pin as ?owered from poe indicator not applicable as power is delivered through the hot swap interface in both poe and faux modes. supported. transient protection excellent due to active mosfet current limit. fair due to passive resistor current limit. the term ?uxiliary dominance mentioned in table 3 means that when the auxiliary power source is connected, it will always power the pd regardless of the state of poe power. ?ux dominance is achievable only with the raux option, as noted in the table. if the pd is not designed for aux dominance, either the faux or raux power sources will deliver power to the pd only under the following two conditions: (i) if auxiliary power is applied before poe power, it will prevent the pds detection by the pse and will supply power indefinitely. this occurs because the poe input bridge rectifiers will be reverse bi- ased, so no detection signature will be observed. under this condition, when the auxiliary supply is removed, power will not be maintained because it will take some time for the pse to perform signature detection and classification before it will supply power. (ii) if auxiliary power is applied after poe power is already present but has a higher voltage than poe, it may assume power delivery responsibility. under the sec- ond case, if the supplied voltages are comparable, the load current may be shared inversely proportional to the respec- tive output impedances of each supply. (the output imped- ance of the pse supply is increased by the cable series resistance). if poe power is applied first and has a higher voltage than the non-dominant aux power source, it will continue power- ing the pd even when the aux power source becomes available. in this case, should poe power be removed, the auxiliary source will assume power delivery and supply the dc-dc loads without interruption. if either faux or raux power is supplied prior to poe power, it will prevent the recognition of the pd by the pse. consequently, continuity of power delivery cannot be guar- anteed because the poe supply will not be present when auxiliary power is removed. faux option with the faux option, the lm5072 hot swap mosfet pro- vides inrush and dc current limit protection for the auxiliary power source. to select the faux configuration for an aux- iliary voltage lower than nominal poe voltages, the icl_faux pin must be forced above its high threshold to override the vin uvlo function. note that when the icl_faux pin is pulled high to override vin uvlo, it also overrides the inrush current limit programmed by r icl ,if present. in this case, the inrush current will revert back to the default 150 ma limit. pulling up the icl_faux pin will increase the default dc current limit to 540 ma. this increase in dc current limit is necessary because higher current is required to support the pd output power at the lower input potentials observed with auxiliary sources. in cases where the auxiliary supply volt- age is comparable to the poe voltage, there is no need to pull-up the icl_faux pin to override vin uvlo, and the default dc current limit remains at 440 ma. however, if the dc current limit is externally programmed with r dccl , the condition of the icl_faux pin will not affect the pro- grammed dc current limit. in other words, programmed dc current limit can be considered a ?ard limit that will not vary in any configuration. raux option the raux option is desirable when the auxiliary supply voltage is significantly lower than the poe voltage or when aux dominance is desired. the inrush and dc current limits of the lm5072 do not protect or limit the raux power source, and an additional resistor in the raux input path will be needed to provide transient protection. to select the raux option without aux dominance, simply pull up the raux pin to the auxiliary power supply voltage through a high value resistor. depending on the auxiliary supply voltage, the resistor value should be selected such that the current flowing into the raux pin is approximately 100 ? when the pin is mid-way between the lower and upper raux thresholds (approximately 4v). for example, with an 18v non-dominant rear auxiliary supply, the pull up resistor should be: if the pse load capacity is limited and insufficient, aux dominance will be a desired feature to off load poe power for other pds that do not have auxiliary power available. aux dominance is achieved by pulling the raux pin up to the auxiliary supply voltage through a lower value ( ~ 5k ? ) resis- tor that delivers at least 250 ? into the raux pin. when this higher raux current level is detected, the lm5072 shuts down the pd interface. in aux dominant mode, the auxiliary power source will supply the pd system as soon as it is applied. pd operation will not be interrupted when the aux power source is connected. the poe source may or may not lm5072 www.national.com 17
raux option (continued) actually be removed by the pse, although the dc current from the network cable is effectively reduced to zero ( < 150 ?). ieee 802.3af requires the ac input impedance to be greater than 2 m ? to ensure poe power removal. this condition is not satisfied when the auxiliary power source is applied. the pse may remove power from a port based on the reduction in dc current. this is commonly known as dc maintain power signature (dc mps), a common feature in many pse systems. the high voltage startup regulator of the pwm controller does not have low dropout capability and will not be able to provide v cc when the potential from vin to rtn is less than 14.5v (no external v cc load). in this case, the auxiliary voltage should supply v cc directly via diode or-ing to en- sure successful startup. when using the raux configuration, the positive potential connection of the 0.1 ? signature capacitor should be moved from vin to rtn/artn as shown in figure 11. this provides a high frequency, low impedance path for the ics substrate during rear auxiliary opration. placing the capacitor here will not affect signature mode. it should be noted that rear auxiliary non-dominance does not imply poe dominance. poe dominance is difficult to achieve in any poe system if continuity of power is desired. when the poe voltage appears, the pse and pd interface must continue delivering load current in addition to charging the input capacitor bank from the auxiliary voltage to the poe voltage. the situation is further complicated by the fact that for a given delivered power level, the load current is much higher at the lower input voltages typically used in auxiliary supplies. as is the case during any inrush sequence, very high power is dissipated in the hot swap mosfet. conse- quently, attempting to achieve inrush completion while deliv- ering load current is highly ill advised. lastly, current deliv- ered to the system may be limited by the pse, the pd, or both. a note about faux and raux pin false input state detection the icl_faux and raux pins are used to sense the pres- ence of auxiliary power sources. the input voltage of each pin must remain low when the auxiliary power sources are absent. however, the or-ing diodes feeding the auxiliary power are not ideal and leak reverse current that can flow from the poe input to both the icl_faux and raux pins. when poe power is applied, these leakage currents may elevate the potentials of the icl_faux and raux pins to false logic states. one of two failure modes may be observed when the power diode feeding the front auxiliary input leaks excessively. first, the current may corrupt the inrush current limit pro- gramming, if that feature has been implemented. second, the leakage current may elevate the voltage on the pin to the icl_faux input threshold, which will force uvlo release. this would certainly interrupt any attempt by the lm5072 pd interface to perform the signature or classification functions. when the power diode that feeds the rear auxiliary input leaks, the false signal could imply a rear auxiliary supply is present. in this case, the internal hot swap mosfet will be turned off. this would of course block poe power flow and cause the circuit to prevent startup. this leakage problem at the control input pins can be easily solved. as shown in figure 12, an additional pull-down re- sistor (rpd) across each auxiliary power control input pro- vides a path for the diode leakage current so that it will not create false states on the icl_faux or raux pins. high voltage startup regulator the lm5072 contains a startup bias regulator that allows the vin pin to be connected directly to poe network voltages as high as 100v. the regulator output is connected to the vcc pin, providing an initial dc bias voltage of 7.7v nominal to start the pwm controller. the regulator is internally current limited to no less than 15 ma to prevent excessive power dissipation. for v cc voltage stability and noise immunity, a capacitor ranging between 0.1 ? to 10 ? is required be- tween the vcc and artn pins. though the current capabil- ity of the regulator exceeds the requirements of the ic, no external dc load drawing more than 3 ma should be applied to the output. a small amount of current for a ?owered from poe indicator led (see power good section) is acceptable. after the dc-dc converter reaches steady state operation, the v cc voltage is typically elevated by an auxiliary winding of the power transformer. the sustained v cc voltage should be greater than 8.1v to guarantee the current supplied by the startup regulator is reduced to zero. increasing the vcc pin voltage above the regulation level of the startup regulator automatically disables the regulator, thus reducing the power dissipation inside the lm5072. the power savings can be significant as many high voltage mosfets require a rela- tively large amount of gate charge and the gate drive current adds directly to the v cc current draw. av cc under-voltage lock-out circuit monitors the v cc volt- age to prevent the pwm controller from operating as the v cc voltage rises during startup or falls during shutdown. the pwm controller is enabled when the v cc voltage rising edge exceeds 7.6v and disabled when the v cc voltage falling edge drops below 6.25v. error amplifier the lm5072 contains a wide-bandwidth, high-gain error am- plifier to regulate the output voltage in non-isolated applica- tions. the amplifiers non-inverting input is set to a fixed reference voltage of 1.25v, while the inverting input is con- nected to the fb pin. the open-drain output of the amplifier is connected to the comp pin, which is pulled up internally throug ha5k ? resistor to an internal 5v bias voltage. feedback loop compensation can be easily implemented by placing the compensation network, represented by ?comp? between the fb and comp pins as shown in figure 13. 20184629 figure 12. bypassing resistor ? prevents false icl_faux and raux pin signaling lm5072 www.national.com 18
error amplifier (continued) for isolated applications, the error amplifier function is lo- cated on the isolated secondary side. the lm5072s error amplifier can be disabled by connecting the fb pin to the artn pin. as shown in figure 14, an opto-coupler is nor- mally used to send the feedback signal across the isolation boundary to the comp pin. the internal pull-up resistor on the comp pin now serves as the pull-up bias for the opto- coupler transistor. current sense and limit the lm5072 cs pin senses the transformer primary current signal for current mode control and current limiting of the supply. as shown in figure 15, the current sense function can be fulfilled by a simple sense resistor r sense inserted between the rtn and the source of the primary mosfet switch. the r sense resistor should be non-inductive, and a low pass filter should be used to reject the switching noise on the sensed signal. a simple rc filter using 100 ? and1nfis typically sufficient. the filter capacitor must be located close to the cs and artn pins. in order to prevent noise propa- gation and to improve the noise immunity of the current sense, it is very important to minimize the return path of the current sense signal. this is accomplished with direct con- nection to the artn pin and a single point connection to the rtn pin on the pc board layout. the current sense signal is also used for cycle-by-cycle over-current protection. when the cs pin signal exceeds 0.5v, the pwm pulse of that cycle will be immediately termi- nated. the desired cycle-by-cycle over-current protection level is achieved by selecting the proper value of current sense resistor that produces 0.5v at the cs pin. for the lm5072-80, the slope compensation reduces the current limit threshold by about 20% maximum at the 80% maximum duty cycle. the typical current sense waveform as shown in figure 16 has a spike at the leading edge. this spike is mainly caused by the large gate drive current that flows through the current sense resistor at turn-on (up to 0.8a). the reverse recovery of the rectifier diode on the secondary side and the cross conduction of the primary mosfet and sync mosfet (if used) may also contribute to this leading edge spike. with a relatively small external rc filter, this spike can still cause a false over-current condition that terminates the pwm output pulse. to avoid this problem, an internal blanking circuit is provided within the lm5072 as shown in figure 15. an internal mosfet is turned on to short the cs pin to artn at the end of each cycle. this mosfet switch remains on for an additional 65ns after the beginning of the next pwm cycle, thus blanking out the leading edge spike on the cur- rent sense signal. soft-start the lm5072 incorporates a soft-start feature which forces the pwm duty cycle to grow progressively during startup such that the output voltage increases gradually to the steady state level. the soft-start process reduces or pre- vents both the surge of inrush current and the associated overshoot of the output voltage during startup. the lm5072 achieves soft-start using an internal 10 ? current source to charge an external capacitor connected to the ss pin. the capacitor voltage limits the voltage at the comp pin which directly controls the pwm duty cycle. the rate of the soft- start ramp can be adjusted by varying the value of the 20184630 figure 13. internal error amplifier ? used for non-isolated output applications 20184631 figure 14. the internal error amplifier ? bypassed in isolated output applications 20184632 figure 15. current sense schemes 20184633 figure 16. typical current sense waveform having a leading edge spike lm5072 www.national.com 19
soft-start (continued) external capacitor. note that the slope of the supplys output voltage is influenced by the load condition and the total output capacitance of the supply, as well as the soft-start programming. the supply should be started slowly enough such that the input current is limited below the hot swap mosfet dc current limit. gate driver and maximum duty cycle limit the lm5072s gate drive (out) pin can source and sink a peak current of 800 ma directly to the gate of the dc-dc converters power mosfet switch. to serve a variety of applications, the lm5072 is available with two options for maximum pwm duty cycle. the lm5072-80 operates at duty cycles up to 80% while the lm5072-50 limits the pwm duty cycle to 50%. oscillator, shutdown and sync capability the lm5072 requires a single external resistor connected between the rt and artn pins to set the oscillator fre- quency (f osc ). the r t timing resistor should be located very close to the ic and connected directly to the rt and artn pins. the following equation describes the relation- ship between f osc and the r t resistor value: the lm5072 can also be synchronized to an external clock signal with a frequency higher than the programmed oscilla- tor frequency determined by the r t resistor. the clock signal should be coupled into the rt pin through a 100 pf capaci- tor, as shown in figure 17. successful synchronization re- quires the peak voltage of the sync pulse signal to be greater than 3.7v at the rt pin, and pulse width between 15 and 150 ns (set by external components). the r t resistor is always required, whether the oscillator is operated in ?ree-running mode or with external synchronization. special attention should be paid to the relationship between the oscillator frequency and the pwm switching frequency. for the lm5072-50 version, the programmed oscillator fre- quency is internally divided by two in order to facilitate the 50% duty cycle limit. the pwm output switching frequency is therefore one half of the programmed oscillator frequency. the frequency divider is not used in the lm5072-80 and therefore the pwm output frequency is the same as the oscillator frequency. these relationships also apply to exter- nal synchronization frequency versus pwm output fre- quency. pwm comparator / slope compensation the pwm comparator produces the pwm duty cycle by comparing the current sense ramp signal with an error volt- age derived from the error amplifier output. the error ampli- fier output voltage at the comp pin is offset by 1.4v and then further attenuated by a 3:1 resistor divider before it is presented to the pwm comparator input. the pwm duty cycle increases with the voltage at the comp pin. the controller output duty cycle reduces to zero when the comp pin voltage drops below approximately 1.4v. for duty cycles greater than 50%, current mode control loops are subject to sub-harmonic oscillation. this instability can be eliminated by adding an additional fixed slope voltage ramp signal to the current sense signal. this technique is commonly known as ?lope compensation? for the lm5072-80 version with its maximum duty cycle of 80%, slope compensation is integrated by injecting a 45 a current ramp from the oscillator into the current sense signal path (see figure 2). the 45 ? peak ramping current flows through an internal 2 k ? resistor to produce a fixed voltage ramp at the pwm comparator input. additional slope com- pensation may be added by increasing the source imped- ance of the current sense signal with an external resistor between the cs pin and the source of the current sense signal. the feature is disabled for the lm5072-50 version because the duty cycle is limited to 50% and slope compen- sation is not required. thermal protection the lm5072 includes internal thermal shutdown circuitry to protect the ic in the event the maximum junction tempera- ture is exceeded. this circuit prevents catastrophic over- heating due to accidental overload of the hot swap mosfet or other circuitry. typically, thermal shutdown is activated at 165?c, causing the hot swap mosfet and classification regulator to be disabled. the pwm controller is disabled after the pgood timer has expired. thermal limit is not enabled unless the module is being powered through the front end and the hot swap mosfet is enhanced. v cc current limit provides an adequate level of protection for this 15 ma regulator. the thermal protection is non-latching, therefore after the temperature drops by the 25?c nominal hysteresis, the hot swap mosfet is re-activated and a soft-start is initiated to restore the lm5072 to normal opera- tion. if the cause of overheating has not been eliminated, the circuit will hiccup in and out of the thermal shutdown mode. pcb layout guidelines before processing the printed circuit board (pcb) layout, the engineer should make all necessary adjustments to the schematic to suite the application. the reader may notice that the lm5072 evaluation board is designed with dual outputs, both faux and raux power options, and some re-configuration flexibility features (refer to figure 19). how- ever, many devices can be removed for a particular applica- tion. recommendations on simplifying figure 19 to suit a given application are as follows: 1. when selecting the faux power option only, delete c3, d1, d2, j3, p3, p4, r1, r2, r13, and r29. 20184635 figure 17. oscillator synchronization implementation lm5072 www.national.com 20
pcb layout guidelines (continued) 2. when selecting the raux power option only, delete c1, d3, d7, j2, p1, p2 and r6. 3. when neither faux nor raux power options are se- lected, delete all the parts mentioned in (1) and (2) above. 4. when only a single output is required, delete c11 through c14, c17, d8, j6, j7, l2, r10 and z4. modify t1 design to delete the unwanted second output winding and increase the copper used for the single output wind- ing. this re-configuration should make use of the spare pins of the transformer. 5. r24 should be deleted from the schematic completely, being replaced by a short connection for an isolated application, or by an open for a non-isolated application. 6. jumpers p5 and p6 (figure 20) should be deleted from the schematic completely, being replaced by a short connection for an isolated application, or by an open for a non-isolated application. 7. when the output is non-isolated, delete c20, c22, c25, r7, r11, r16, r17, r24, u2, and u3. replace c28 with a short connection, and replace p5 and p6 with short connections. 8. one may also modify the number of input and output capacitors to achieve a more optimized design. consider the following when starting the pcb design: 1. try to use both sides of the pcb for part placement to facilitate both layout and routing. 2. place the power components in a pattern that minimizes the lengths of the high current paths on the pcb. 3. place the lm5072 and its critical peripheral parts closely. bypass capacitors and transient protection ele- ments should be near the lm5072. 4. route the critical traces first, including both power and signal traces. make the length of the trace as short as possible, and avoid excessive use of via holes. 5. pay attention to grounding issues. each reference ground should be a copper plane or island. use via holes if necessary for direct connections of devices to their appropriate return ground plane or island. identify the following ground returns: primary power return com: c4, c5, c6, r14, r15, r29, c3, p4, j3-pins 2 and 3, u1-pin 8, c28, and c29 are all returned to the com ground plane. primary control signal return, a ground return island: c19, t1-pin 2, c23, u2-pin 3, r24, c26, c21, and u1-pin 16 are all returned to this island, and the island should be single point connected to the com ground plane. secondary power return ignd: t1-pins 6 and 7, c7 through c10, c12 through c17, c28, z4, j5, and j7 are all returned to the ignd ground plane. secondary control signal return, a ground return is- land: r18, u3 and c20 are all returned to this island, and the island should be single point connected to the ignd ground plane. also consider the following during pcb layout and routing. 1. place the following power components in each group as close as possible: c4, c5 (if used), the primary winding of t1, q1, and r14/r15. the high frequency switching current (pulse current) flows through these parts in a loop. the physical area enclosed by the loop should be as small as pos- sible. d5, c7 through c10, and the secondary winding of t1 for the main output. the high frequency switching cur- rent for the main output rail flows through these parts in a loop. the physical area enclosed by the loop should be as small as possible. d8, c12 and c13, and the secondary winding of t1 for the second output, if used. the high frequency switching current for the second output rail flows through these parts in a loop. the physical area enclosed by the loop should be as small as possible. l3, c15, c16, j4 and j5 (if posts are used). l3 should also be as close as possible to the capacitor bank consisting of c7 through c10 in order to minimize the conduction losses on the pcb. ceramic capacitor c15 should be placed directly at the output port. l2, c14, c17, z4, j6 and j7 (if posts are used) for the second output rail. l2 should also be as close as pos- sible to c12 and c13 in order to minimize the conduction losses on the pcb. ceramic capacitor c14 should be directly placed at the output port 2. u1 (lm5072) should be placed close to q1 in the orien- tation such that the gate drive output pin (out, pin 9) is close to q1s gate. 3. (iii) z2 and c27 must be placed directly across the vin and vee pins for best protection against input tran- sients. in a rear auxiliary application, c27 should be removed and c29 should be installed very close to the rtn and vee pins. 4. c19 should be placed directly across the vcc and artn pins. 5. c23 should be placed directly across the cs and artn pins. 6. r21 should be placed directly across the rt and artn pins. 7. c26 should be placed directly across the ss and artn pins. 8. c21 should be placed directly across the npgood and artn pins. 9. r25 should be directly routed from the output port. 10. r9 should be directly routed from r14/r15. 11. d6 and z1 should be placed to achieve the shortest connection from c4 or c5 to the drain pad(s) of q1 for better snubbing. 12. c2 and r4 should be placed to achieve the shortest connection across d5. 13. q1, d5, d8, and u1 (lm5072) should be installed on thermal pads having adequate thermal vias down through all pcb layers and an exposed thermal pad on the other side of the pcb. 14. avoid spiral trace pattern. 15. avoid placing switching traces near any traces in the regulator feedback loop. 16. pay attention to trace width. try to make the power traces as wide as possible. conversely, do not make signal traces wider than needed. after the first placement and routing is completed, make necessary modifications to optimize the design. lm5072 www.national.com 21
application example #1 figure 18 shows an application example of a single isolated output solution for the pd. both front auxiliary (faux) and rear auxiliary (raux) power options are given, although only one option may be needed in practice. note that for the raux option, d2 is only installed when the supply voltage of the auxiliary power source would cause the v in voltage to be below 14.5v. application example #2 figure 19 shows an example of an isolated, dual-output solution for the pd. the 3.3v output is tightly regulated while the 5v output is cross-regulated. both front auxiliary (faux) and rear auxiliary (raux) power options are given, although only one option may be needed in practice. note that for the raux option, d2 is only installed when the supply voltage of the auxiliary power source is lower than 14.5v. 20184636 figure 18. pd with isolated, single output solution 20184637 figure 19. pd with isolated, dual output solution lm5072 www.national.com 22
application example #3: figure 20 shows an application example of the non-isolated version of figure 18 . this non-isolated version saves many parts used in the isolated feedback example shown in figure 18. similar simplification also applies to the non-isolated version of figure 19. application example #4 figure 21 shows an application example of a pd solution using the buck topology. q2, a dual pnp transistor, is employed in the output voltage sensing to achieve temperature compensation for the regulated output. 20184638 figure 20. pd solution with non-isolated flyback topology 20184639 figure 21. pd solution with buck topology lm5072 www.national.com 23
physical dimensions inches (millimeters) unless otherwise noted package number mxa16a national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications. for the most current product information visit us at www.national.com. life support policy national? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. banned substance compliance national semiconductor manufactures products and uses packing materials that meet the provisions of the customer products stewardship specification (csp-9-111c2) and the banned substances and materials of interest specification (csp-9-111s2) and contain no banned substances as defined in csp-9-111s2. leadfree products are rohs compliant. national semiconductor americas customer support center email: new.feedback@nsc.com tel: 1-800-272-9959 national semiconductor europe customer support center fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer support center email: ap.support@nsc.com national semiconductor japan customer support center fax: 81-3-5639-7507 email: jpn.feedback@nsc.com tel: 81-3-5639-7560 www.national.com lm5072 integrated 100v power over ethernet pd interface and pwm controller with aux support

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